1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device and, more particularly, to a method of forming a via contact structure using a dual damascene process.
A claim of priority is made to Korean Patent Application No. 10-2004-0052056, filed on Jul. 5, 2004, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
As semiconductor devices become increasingly integrated, a metallization process stands out as a factor limiting the performance and reliability of the semiconductor devices. In particular, the metallization process often contributes to resistance-capacitance (RC) delay and electromigration (EM) problems. In order to address these problems, a copper interconnection and a low-k dielectric layer are commonly applied to the semiconductor device, and a damascene process is used to form the copper interconnection.
The damascene process is widely used to form an upper metal interconnection which is electrically connected to a lower metal interconnection. The upper metal interconnection fills a via hole and a trench region which are formed in an inter-metal dielectric layer. The via hole is formed to expose a predetermined region of the lower metal interconnection, and the trench is formed to have a line-shaped groove spanning the via hole. Accordingly, the via hole and the trench are formed by two separate etching processes. Such a damascene process is called a dual damascene process.
FIGS. 1A to 1F are cross-sectional views illustrating a conventional method of forming a via contact structure.
Referring to FIG. 1A, a lower insulating layer 10 is formed on a semiconductor substrate 5. A damascene process is used to form a lower interconnection 12 in lower insulating layer 10. Lower interconnection 12 is typically formed of a copper layer or a tungsten layer.
An etch stop layer 15 and an insulating interlayer 17 are sequentially formed on lower insulating layer 10 and lower interconnection 12. Etch stop layer 15 is formed of a silicon nitride layer. Insulating interlayer 17 is formed of a single low-k dielectric layer in order to enhance an operating speed of the semiconductor device and to prevent an interface from forming in insulating interlayer 17. The single low-k dielectric layer is typically formed of a silicon oxide layer containing carbon, fluorine or hydrogen. For example, the low-k dielectric layer commonly comprises a SiOC layer, a SiOCH layer or a SiOF layer.
Insulating interlayer 17 is often damaged during a subsequent fabrication process, thereby degrading its low-k dielectric characteristics. Accordingly, a capping oxide layer 20 is formed on insulating interlayer 17 in order to protect the electrical characteristics thereof. Capping oxide layer 20 is typically formed of a tetra ethyl orthosilicate (TEOS) layer or an undoped silicate glass (USG) layer. The surface of insulating interlayer 17 is typically altered by the formation of capping oxide layer 20 in an oxygen gas atmosphere, leaving an interface layer 17a during the formation of capping oxide layer 20. Where insulating interlayer 17 is formed of a SiOC layer, oxygen gas from capping oxide layer 20 reacts with carbon in the SiOC layer, thereby producing CO2 gas. This creates interface layer 17a, which is not densely formed.
Capping oxide layer 20, interface layer 17a, and insulating interlayer 17 are sequentially patterned to form a preliminary via hole 25 exposing a portion of etch stop layer 15 on lower interconnection 12.
Referring to FIG. 1B, a sacrificial layer 30 filling preliminary via hole 25 is formed on the semiconductor substrate having preliminary via hole 25. Sacrificial layer 30 is formed of a layer having a wet etch selectivity relative to insulating interlayer 17. Sacrificial layer 30 is formed in order to prevent preliminary via hole 25 from being deformed in a subsequent process.
Referring to FIG. 1C, sacrificial layer 30, capping oxide layer 20, interface layer 17a, and insulating interlayer 17 are sequentially patterned by photolithography and etching processes to form a trench region 35 spanning preliminary via hole 25. Following the formation of trench region 35, a sacrificial layer 30a remains in preliminary via hole 25.
Referring to FIG. 1D, sacrificial layer 30a in preliminary via hole 25 and sacrificial layer 30 on insulating interlayer 17 are removed. Sacrificial layers 30 and 30a are removed using a wet etch solution. As a result, the portion of etch stop layer 15 is exposed. Sacrificial layer 30a has a wet etch selectivity relative to insulating interlayer 17, thus preventing the surface of insulating interlayer 17 from being etched. However, due to certain characteristics of interface layer 17a, which is not densely formed, interface layer 17a is also etched in the process of wet etching sacrificial layers 30 and 30a. As a result, an undercut defect “A” occurs below capping oxide layer 20. Where undercut defect “A” is severe, interface layer 17a is often completely etched, thereby creating a region “B” where capping oxide layer 20 is completely removed.
Referring to FIG. 1E, the portion of etch stop layer 15 is removed to form a final via hole 25a exposing lower interconnection 12. Etch stop layer 15 is removed by dry etching. A portion of insulating interlayer 17 is also commonly etched in the process of etching etch stop layer 15. In particular, partial etching is typically carried out below where undercut defect “A” has occurred, thereby forming an extended undercut defect “A1”.
Referring to FIG. 1F, an upper metal layer is formed on the semiconductor substrate having final via hole 25a. The upper metal layer is generally formed by sequentially forming a barrier metal layer 40 and a metal layer 45. Barrier metal layer 40 is typically formed of a TaN layer or a TiN layer, and metal layer 45 is typically formed of a copper layer. Metal layer 45 is formed as follows. A copper (Cu) seed layer 42 is first formed on barrier metal layer 40 using a sputtering method and copper seed layer 42 is used to form metal layer 45 using a plating method. Because copper seed layer 42 is formed using the sputtering method, copper seed layer 42 is not formed where extended undercut defect “A1” has occurred. Thus, where metal layer 45 is formed using the plating method, a void defect “C” commonly occurs near extended undercut defect “A1” due to the fact that copper seed layer 42 did not properly form at that location. Void defect “C”, causes the resistance of a contact structure to increase.
What is needed, therefore, is a method of forming a via contact structure which is capable of preventing undercut defect “A1” and void defect “C” from occurring.